Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins's Analog-Baseband Architectures And Circuits For Multistandard PDF

By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

ISBN-10: 1402064322

ISBN-13: 9781402064326

ISBN-10: 1402064330

ISBN-13: 9781402064333

With the prior few decade efforts on lithography and integrated-circuit (IC) applied sciences, very inexpensive microsystems were effectively constructed for lots of varied functions. the fashion in instant communications is towards making a networkubiquitous period within the future years. Many extraordinary possibilities and demanding situations, resembling layout for multi-standardability and low-voltage (LV) compliance, are quickly changing into the mainstream instructions in wireless-IC learn and improvement, provided that the previous can provide the simplest connectivity between diverse networks, whereas the latter can facilitate the expertise migration into the sub-1-V nanoscale regimes for additional fee and gear aid.

Analog-Baseband Architecturees and Circuits presents architectural and circuit innovations for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the ebook reports the actual layer standards of recent instant verbal exchange criteria, offers the basic tradeoffs excited by transceiver structure choice, and offers case reports of the cutting-edge multistandard transceivers, the place the main options strengthened are highlighted and mentioned. A statistical precis (with a hundred+ references stated) of so much used transmitter and receiver architectures for contemporary conversation criteria is equipped. all of the references are citied from the best boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.

The moment half makes a speciality of the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection process is disclosed. It, during the reconfiguration of receiver and transmitter analog basebands, permits not just a leisure of the RF frequency synthesizer’s and native oscillator’s layout requirements, but in addition a good multistandard compliance via synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the main is established in few layout examples. one in every of them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but additionally includes a flexible-IF topology, a different 3D-stack floorplan, and a selected layout technique for prime testability and routability.

The 3rd half bargains with the circuit layout. as well as the methodical description of many LV circuit innovations, three tailormade LV-robust useful blocks are awarded. They contain: 1) a double-quadrature-downconversion clear out (DQDF) – it realizes at the same time clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon region required for figuring out a wide time consistent on chip whereas maximizing its highpass-pole switchability for speedy dc-offset transient.

The final half provides experimental result of the three tailored development blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS procedure. formerly untold on-/off-chip co-setup for either full-chip and construction blocks measurements are defined. not just the development blocks have effectively prolonged the cutting-edge boundary by way of sign bandwidth and provide voltage, the analog-baseband IC has been thus far the lowest-voltage-reported answer for IEEE 802.11a/b/g WLAN receivers.

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Quad-Band GSM/GPRS/EDGE Polar Loop Transmitter,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 186–187, Feb. 2004. 20] S. T. 5V 28mA Fully-Integrated Fast-Locking Quad-Band GSMGPRS Transmitter with Digital Auto-Calibration in 130nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 188–189, Feb. 2004. 21] M. , “A Polar Modulator Transmitter for EDGE,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.

57–60, Sept. 2000. 28] J. 7dB NF Direct Conversion Receiver for 3G WCDMA,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 284–285, Feb. 2001. 29] M. Ugajin, J. Kodate and T. Tsukahara, “A 1V 12mW 2GHz Receiver with 49dB Image Rejection in CMOS/SIMOX,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 288–289, Feb. 2001. 30] L. Der and B. Razavi, “A 2GHz CMOS Image-Reject Receiver with Sign-Sign LMS Calibration,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.

11a, b and g. 4-GHz and 5-GHz bands were implemented with shared mixers, channel-selection filters and VGAs. One frequency synthesizer and one VCO shares between different modes, RX and TX. The LO leakage in the transmitter is eliminated by applying a LO-leakage calibration loop. The lowpass channel-selection filter in both RX and TX is of fifth-order and offers a variable gain feature. A successive switching technique implemented in the dc-offset cancellation loop is to improve the settling time in the RX gain adjustment.

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Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins


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