By M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner
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We try to minimize possible conflicts by scheduling the longest paths first. By doing this, operations on long paths would be more likely to be scheduled much later than their yet unscheduled predecessors in shorter paths. Although our algorithm is locally optimal, it might not yield a globally optimal schedule. This lack of optimality is related to the correction passes. Although we schedule a given path optimally under the given conditions, it does not mean that the final global schedule will require this path to be scheduled within the shortest time.
Power analysis of gated pipeline registers. In Proceedings of the Twelfth Annual IEEE International ASIC/SOC Conference. 281–285. Received January 2003; revised August 2003; accepted March 2004 ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 1, January 2005. A Scheduling Algorithm for Optimization and Early Planning in High-Level Synthesis SEDA OGRENCI MEMIK Northwestern University RYAN KASTNER University of California, Santa Barbara ELAHEH BOZORGZADEH University of California, Irvine and MAJID SARRAFZADEH University of California, Los Angeles Complexities of applications implemented on embedded and programmable systems grow with the advances in capacities and capabilities of these systems.
At that point we will need the correction pass and push operation Op5 by one control step to accomodate time for Op2 . Similarly, in the consequent steps of the algorithm, a correction pass will be required before scheduling Op3 and Op4 . This shows that we might need corrections proportional to V , which is the number of operations in the DFG. Note that, in each step, the scheduling decision of at least one node (the node with no parent) will be finalized. Therefore, we will not need more than V correction passes.
ACM Transactions on Design Automation of Electronic Systems (January) by M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner